;;;
;;;  SPDIF Buffer    ver 1.0
;;;                                               2003/10/12  UENO Tomohiro
;;;
;;;  for ATMEL AVRStudio 4.07
;;;
;;;  Device   Micro computer : ATMEL    AVR 90S8515 with external Xtal 10MHz

.include	"8515def.inc"

.def	tmp		= R16

.def	in_addr_high 	= R17
.def	in_addr_low 	= R18
.def	out_addr_high 	= R19
.def	out_addr_low 	= R20

.def	prev_clk	= R21
.def	current_clk	= R22
.def	no_in_counter	= R23
.def	led_high	= R24
.def	led_low		= R25

.def	c0x00		= R00
.def	c0x01		= R01
.def	out_skip_flag	= R02
.def	in_init_flag	= R03
.def	out_init_flag	= R04
.def	led_mask_flag	= R05

.equ	lrck_in		= 7	; portA
.equ	lrck_out	= 6	; portA
.equ	hc595_g		= 5	; portA
.equ	hc574_clk	= 4	; portA
.equ	led_ovf		= 3	; portA
.equ	led_udf		= 2	; portA

.equ	mask_lrck_in	= 0b10111111
.equ	mask_lrck_out	= 0b01111111

.equ	cs		= 2	; portB
.equ	we		= 1	; portB
.equ	oe		= 0	; portB

	rjmp	reset	; 1 $000 reset vector
	reti		; 2 $001 INT0 
	reti		; 3 $002 INT1 
	reti		; 4 $003 TIMER1 CAPT
	reti		; 5 $004 TIMER1 COMPA 
	reti		; 6 $005 TIMER1 COMPB
	reti		; 7 $006 TIMER1 OVF1 
	reti		; 8 $007 TIMER1 OVF0 
	reti		; 9 $008 SPISTC
	reti		;10 $009 UART RX 
	reti		;11 $00A UART UDRE
	reti		;12 $00B UART TX
	reti		;13 $00C ANA_COMP

RESET:	
	ldi	tmp, high(RAMEND)
	out	SPH, tmp
	ldi	tmp, low(RAMEND)
	out	SPL,tmp

	; portA initialize
	ldi	tmp,0x3f	; bit7-6:input , bit5-0;output
	out	DDRA,tmp
	ldi	tmp,0x00	; no pullup
	out	PORTA,tmp

	; portB initialize
	ldi	tmp,0xff	; output
	out	DDRB,tmp
	ldi	tmp,0x00	; no pullup
	out	PORTB,tmp

	; portC initialize
	ldi	tmp,0xff	; output
	out	DDRC,tmp
	ldi	tmp,0xff	
	out	PORTC,tmp

	; portD initialize
	ldi	tmp,0xff	; output
	out	DDRD,tmp
	ldi	tmp,0xff	
	out	PORTD,tmp

	sbi	PORTB,cs
	sbi	PORTB,oe
	sbi	PORTB,we

	cbi	PORTA,led_ovf
	cbi	PORTA,led_udf
	ldi	led_low,0xff
	ldi	led_high,0xff
	mov	led_mask_flag,c0x01

	ldi	tmp,0
	mov	c0x00,tmp
	ldi	tmp,1
	mov	c0x01,tmp

	in	prev_clk,PINA

init:
	ldi	in_addr_high,0
	ldi	in_addr_low,0
	ldi	out_addr_high,0x80
	ldi	out_addr_low,0	

	mov	in_init_flag,c0x01
	mov	out_init_flag,c0x01
	mov	out_skip_flag,c0x01

	
loop:
	in	current_clk,PINA
	mov	tmp,prev_clk
	eor	tmp,current_clk
	sbrc	tmp,lrck_in
	rjmp	in_check
	sbrc	tmp,lrck_out
	rjmp	out_check
	rjmp	loop

in_check:
	mov	tmp,current_clk
	cbr	tmp,~(1<<lrck_in)
	breq	in_0
in_1:
	sbr	prev_clk,1<<lrck_in
	tst	in_init_flag
	breq	in_end
	inc	in_addr_low
	mov	in_init_flag,c0x00
	rjmp	in_end
in_0:
	cbr	prev_clk,1<<lrck_in
in_end:
	tst	led_mask_flag
	brne	PC+9
	cp	in_addr_high,out_addr_high
	brne	PC+7
	cp	in_addr_high,out_addr_high
	brne	PC+5
	ldi	led_low,0xff
	ldi	led_high,0xff
	cbi	PORTA,led_ovf
	mov	led_mask_flag,c0x01

	out	PORTC,in_addr_high
	out	PORTD,in_addr_low
	cbi	PORTA,hc595_g
	cbi	PORTB,cs
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	cbi	PORTB,we
	sbi	PORTB,we
	sbi	PORTB,cs
	sbi	PORTA,hc595_g
	add	in_addr_low,c0x01
	adc	in_addr_high,c0x00

	ldi	no_in_counter,0
	sbrc	in_addr_high,7
	clr	out_skip_flag
	rjmp	loop

out_check:
	tst	out_skip_flag
	brne	loop
	mov	tmp,current_clk
	cbr	tmp,~(1<<lrck_out)
	breq	out_0
out_1:	
	sbr	prev_clk,1<<lrck_out
	tst	out_init_flag
	breq	out_end
	inc	out_addr_low
	mov	out_init_flag,c0x00
	rjmp	out_end
out_0:
	cbr	prev_clk,1<<lrck_out
out_end:
	tst	led_mask_flag
	brne	PC+9
	cp	in_addr_high,out_addr_high
	brne	PC+7
	cp	in_addr_high,out_addr_high
	brne	PC+5
	ldi	led_low,0xff
	ldi	led_high,0xff
	cbi	PORTA,led_udf
	mov	led_mask_flag,c0x01

	out	PORTC,out_addr_high
	out	PORTD,out_addr_low
	cbi	PORTB,cs
	cbi	PORTB,oe
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	cbi	PORTA,hc574_clk
	sbi	PORTA,hc574_clk
	sbi	PORTB,oe
	sbi	PORTB,cs
	add	out_addr_low,c0x01
	adc	out_addr_high,c0x00

	inc	no_in_counter
	cpi	no_in_counter,3
	breq	init2

	mov	tmp,led_low
	or	tmp,led_high
	breq	PC+4
	sub	led_low,c0x01
	sbc	led_high,c0x00
	rjmp	PC+4
	sbi	PORTA,led_udf
	sbi	PORTA,led_ovf
	mov	led_mask_flag,c0x00

	rjmp	loop
init2:
	rjmp	init